1. Field of the Invention
The present disclosure relates to liquid crystal display technology, and more particularly to a liquid crystal device (LCD) and the gate driving circuit thereof.
2. Discussion of the Related Art
FIG. 1 is a circuit diagram of one conventional level transition circuit. FIG. 2 is a timing diagram of the clock signals, selection signals, and voltage reference signals of FIG. 1. As shown in FIG. 1, the level transition circuit 10 is configured for generating the clock signals CK1, CK2, the selection signals LC1, LC2, and the voltage reference signals (VSS). The clock signals CK1, CK2, the selection signals LC1, LC2, and the voltage reference signals (VSS) are configured for driving the shift register circuit. The level transition circuit 10 inputs the high voltage VGH and the low voltage VGL. The high voltage of the clock signals CK1, CK2 and the selection signals LC1, LC2 are VGH, and the low voltage of the clock signals CK1, CK2, the selection signals LC1, LC2 and the voltage reference signals (VSS) are VGL. As shown in FIG. 2, when the low voltage of the clock signals CK1, CK2, the selection signals LC1, LC2, and the voltage reference signals (VSS) are VGL, the thin film transistors (TFTs) of the shift register circuit may not be turned off normally.